This invention relates generally to charge pumps for phase locked loops, and more specifically to a differential input and output charge pump and an associated common mode feedback circuit.
Phase locked loops (PLLs) maintain an output signal in phase relationship to an input signal. Accordingly, PLLs are useful for deriving a clock signal from an incoming digital data stream. Modern digital data communication systems operate at extremely high frequencies at which data bandwidth is at a premium. Providing a clock signal, along with a data signal, inordinately taxes the bandwidth of such systems. Thus, PLLs are used, often as part of a clock recovery unit, to derive a clock signal from incoming data signals.
PLLs generally comprise a phase comparator providing an up signal and a down signal, a charge pump receiving the up signal and down signal, a low pass filter receiving the output of the charge pump, and a voltage or current controlled oscillator. The phase comparator determines if the frequency of the oscillator needs to be increased or decreased. The phase comparator outputs the up signal when the frequency of the oscillator needs to be increased, and outputs the down signal when the frequency of the oscillator needs to be decreased.
The high frequency at which data is communicated in modern data systems, and the need for higher reliability for the transmission of such data, however, places significant requirements and low margins of error on PLLs. One source of errors in PLLs is the charge pump circuitry.
Charge pumps are often comprised of CMOS transistor elements. The CMOS transistor elements often exhibit slight variations in performance due to mechanical manufacturing discrepancies. Such discrepancies often result in variations in the handling of the up and down input signals. Additionally, variations in the power supply used to power or bias the transistor elements also may result in unnecessary variations, or jitter, in the charge pump signal.
One way to improve the performance of a charge pump is to use differential inputs or outputs, as well as to use a feedback circuit based on a common mode signal of the differential outputs. Charge pumps with a differential output utilizing a common mode circuit to reduce fluctuations in the differential outputs are known. Advances in semiconductor device design and manufacturing, however, has resulted in circuitry using decreased voltage levels. Such decreased voltage levels make the use of current sources inside a common mode feedback circuit difficult.
The present invention therefore provides a differential charge pump for a low jitter PLL and a low voltage common mode feedback circuit. The charge pump includes a first signal source responsive to a reference signal and a common mode feedback signal, with the first signal source providing a first signal. A first output signal path is coupled to the first signal source, with the first output signal path providing a path for a first output signal. The first output signal comprises at least a portion of the first signal. The charge pump also includes a first switched signal path coupled with the first signal source. The first switched signal path includes an up signal controlled switch having active and nonactive states, with the state of the up signal controlled switch controlled by an up signal. The first switched signal path provides a path for a first switched signal, the first switched signal being at least a portion of the first signal. The charge pump also includes a second signal source responsive to the reference signal and the common mode feedback signal, with the second signal source providing a second signal. A second output signal path is coupled to the second signal source, with the second output signal path providing a path for a second output signal. The second output signal comprises at least a portion of the second signal. The charge pump also includes a second switched signal path coupled with a second signal source. The second switched signal path includes a down signal controlled switch having active and nonactive states, with the state of the down signal controlled switch controlled by a down signal. The second switched signal path provides a path for a second switched signal, the second switched signal being at least a portion of the second signal. In addition, a common mode circuit is coupled to the first output signal path and the second output signal path. The common mode circuit generates the common mode feedback signal based on a common mode component of the first and second output signals.
In one embodiment the common mode feedback circuit comprises an input differential transistor pair receiving a differential input. The differential transistor pair produces a common mode current. A reference current source, on the other hand, provides a reference current. Coupled to the input differential transistor pair and the reference current source is a current mirror. The current mirror has a first current provided by the reference current, and a second current provided by the common mode current. The current mirror is controlled by the reference current. The common mode feedback circuit additionally comprises a difference wire. The difference wire provides a path for excess current when the differential transistor pair produces a current and magnitude greater than a second current, the second current being the current controlled by the current mirror to be equaled magnitude for the reference current.
Many of the attendant features of this invention will be more readily appreciated as the same becomes better understood by reference to the following detailed description considered in connection with the accompanying drawings.